1. Field of the Invention
The present invention relates to an Electro-Static Discharge (ESD) clamp circuit.
2. Description of the Prior Art
With the advance of the IC industry, the CMOS technologies have been shrunk to the nanometer scale. Because of this, the gate oxide thickness has been scaled down to several nanometers. With such a thin oxide, the gate leakage issue becomes the dominant source of leakage in advanced CMOS technologies. FIG. 1 shows the gate leakage simulation for NMOS and PMOS transistor with size 1 μm/1 μm with 1V-bias and T=25° C. It can be seen in FIG. 1 how the gate leakage issue aggravates with each shrink (i.e. 90 nm, 65 nm to 45 nm) in the CMOS processes.
Since the gate leakage issue impacts drastically in the traditional power-rail ESD protection circuit, the big capacitor used for the RC ESD-transient detection becomes an important source of leakage. The traditional power-rail ESD protection circuit thus is limited thereto.
On the other hand, area reduction is also important for reducing manufacturing costs. The area used by the capacitor in the power-rail ESD protection circuit is usually very large, resulting in very high manufacturing cost. Therefore, besides the leakage current problems, the traditional power-rail ESD protection circuit further encounters the area costing problems.
As the traditional power-rail ESD clamp circuit is a key part of the whole-chip ESD protection, a very typical realization of the power-rail ESD clamp circuit is shown in FIG. 2, which uses a silicon controlled rectifier as the main ESD Clamp. The silicon controlled rectifier is a better choice than a MOSFET for the main clamp device. The RC delay formed by the transistor MCAP and the resistor R is used to detect the fast transient nature of the ESD stress. When an ESD is zapping at VDD, the internal node VRD is initially 0V and starts to rise with the RC time constant. The voltage drop across the resistor R thus turns the MOSFET Mp to trigger the silicon controlled rectifier and discharge the ESD current through a safe path. Nevertheless, under normal circuit operation, the gate leakage through the transistor MCAP (due to the gate leakage effect) causes a voltage drop across the resistor R, thus slightly turning the MOSFET Mp on and adding a second leakage path which increments even more the total leakage current.
Another technique to reduce the leakage in the capacitor has been previously proposed. This circuit, shown in FIG. 3, uses a series of switches to drive the capacitor bottom node to VDD or VSS. Under normal circuit operation, the capacitor bottom node is tied to VDD, so there is no voltage drop across the RC delay, therefore eliminating the leakage current through the capacitor. However, during ESD, the capacitor bottom node is then tied to VSS, so the circuit works similar to the traditional power-rail ESD protection circuit, which results in the same problems.
Therefore, an alternative to the RC-based ESD detection circuit consists on using a series of forward-connected diodes (diode string) and a resistor, such as shown in FIG. 4. Under a positive-to-VSS ESD stress zapping at VDD, the voltage at VDD will start increasing until some voltage when the diodes start conducing. Until then, the node VA remains 0V. When the diodes start conducing, there will be a voltage drop at the resistor R, which will turn Mn on to trigger the silicon controlled rectifier. The diode string threshold voltage is designed to be higher than the power supply voltage, so under normal circuit operation VA remains 0V and Mn is turned off. This circuit presents a relatively large leakage current from drain to gate on the transistor Mn due to gate leakage. However, since the silicon controlled rectifier is connected to the source of the transistor, the trigger current will be reduced because of the voltage drop caused on the substrate resistance of the silicon controlled rectifier, which leads the leakage current and the trigger current trade-off.
On account of above, it should be obvious that there is indeed an urgent need for a circuit which that achieves the ease of use of a layout area without aggravating in leakage current inherent when using a power-rail ESD clamp.